DMP Electronics eBOX-3350MX-AP Manual do Utilizador descarregar pdf (Página 99)

386SX Single Chip PC Jan Yin Chan Electronics Co.,LTD.

DM&P M6117D : System on a chip

Page 98

Jan Yin Chan Electronics Co,. LTD. M6117D 386SX Single Chip PC

8F-1,No.22,Wuchyuan 2RD.,Hsin Chuang city Taipei Hsien, Taiwan, R.O.C. Tel: 886-(02) 2298-0770 Fax: (02) 2299-1883

Meaning of symbols :

Data Flow delay

Input Setup time

Input Hold time

Output Valid delay

Output Float delay

skew1

Clock skew time between BCLK2 and ATCLK

skew2

Clock skew time between OSC14M and CK7M

Notes :

1. Parity data is only recognized in non-CPU memory read cycles, the timing requirements are related to command ending.

2. Parity data are only generated in non-CPU memory write cycles, the timing are related to the stable ISA data. The memory

cycles in notes 2 and 3 refer to the on-board local memory cycles.

3. The timing refers to the generated delay after the CPU stable address.

4. The timing refers to propagating delay from BD to SD.

5. The timing refers to propagating delay from SD to BD.

The following pages show the input waveforms :

Setup, Hold, Valid, Float Delay time description

CLK

Input

signals

Output

signals

Output

signals

Inactive

VALID

Inactive

VALID

Inactive

VALID

Note : 1. For coprocessor and DRAM side signals, CLK = CLK2

2. For ISA side signals, CLK = ATCLK

3. Signal reference level = 1.5 V

4. Environment : loading 50 pF

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DMP Electronics eBOX-3350MX-AP Manual do Utilizador Página 99