DMP Electronics eBOX-3350MX-AP Manual do Utilizador descarregar pdf (Página 102)

Jan Yin Chan Electronics Co.,LTD. 386SX Single Chip PC

M6117D : System on a chip

DM&P

Jan Yin Chan Electronics Co,. LTD. M6117D 386SX Single Chip PC Page 101

8F-1,No.22,Wuchyuan 2RD.,Hsin Chuang city Taipei Hsien, Taiwan, R.O.C. Tel: 886-(02) 2298-0770 Fax: (02) 2299-1883

Appendix

Subject : New Improvement of Power Good Circuit on M6117

Date : October 1, 1997

Part & Version : Total Pages : 4

To : All Distributors & M6117 Customers

From : Fencer J.A. Chen Ext. 5128 / Ali , email: [email protected]

Note : M6117 needs delay of 150ms for PWG signal.

0. Please refer to Fig.1 for PWG circuit.

1. PWG form power supply:

 Power good delay time depends on the power supply spec.

 PWG rise time depends on R8 / C2 value, warm reset delay time depends on C2 / R9 value.

 Please refer to Fig.2 - Fig. 4 for scope timing.

2. PWG form LM393

 PWG rise time, delay time, warm reset delay time all depend on R / C value.

 PWG delay time depends on R5,R6 / C1 value (see table1 for delay time setting), PWG rise time depends on R7 /

C2 value, warm reset delay time depends on C2 & R9 value.

 Please add C1 for LM393 circuit and modify R5 & R6 to 470K & 100K. If we do not modify LM393 circuit for PWG,

there may be some power-on failure on high speed application (such as 40Mhz). This change will insert delay time

for VCC rise to valid voltage.

 Please refer to Fig.5 - Fig. 9 for scope timing.

R5 R6 C1 Delay Time

470K 100K 10U 1080ms

470K 100K 4.7U 350ms

470K 100K 2.2U 306ms

47K 10K 10U 150ms

47K 10K 4.7U 98ms

Table1 LM393 delay time

3. PWG form ADM709MAR

 PWG delay time fix in 184 ms by ADI.

 PWG rise time depends on R7 / C2 value, warm reset delay time depends on C2 / R9 value.

 Please refer to Fig.10 - Fig. 12 for scope timing.

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DMP Electronics eBOX-3350MX-AP Manual do Utilizador Página 102