DMP Electronics eBOX-3350MX-AP Manual do Utilizador Página 48

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Jan Yin Chan Electronics Co.,LTD. 386SX Single Chip PC
M6117D : System on a chip
DM&P
Jan Yin Chan Electronics Co,. LTD. M6117D 386SX Single Chip PC Page 47
8F-1,No.22,Wuchyuan 2RD.,Hsin Chuang city Taipei Hsien, Taiwan, R.O.C. Tel: 886-(02) 2298-0770 Fax: (02) 2299-1883
INDEX 38H default 00H
Bit Description
7~4 Watchdog timer time out report signal
select
0000: Reserved
0001: IRQ3 selected
0010: IRQ4 selected
0011: IRQ5 selected
0100: IRQ6 selected
0101: IRQ7 selected
0110: IRQ9 selected
0111: IRQ10 selected
1000: IRQ11 selected
1001: IRQ12 selected
1010: IRQ14 selected
1011: IRQ15 selected
1100: NMI selected
1101: system reset selected
1110: Reserved
1111: Reserved
3~0 SMI relocate to IRQ
0000: depend on Index 55H setting
0001: Reserved
0010: Reserved
0011: IRQ3 timing support
0100: IRQ4 timing support
0101: IRQ5 timing support
0110: IRQ6 timing support
0111: IRQ7 timing support
1000: Reserved
1001: IRQ9 timing support
1010: IRQ10 timing support
1011: IRQ11 timing support
1100: IRQ12 timing support
1101: Reserved
1110: IRQ14 timing support
1111: Reserved
INDEX 39H default 00H
Bit Description
7~0 Watchdog timer counter value, byte 0
INDEX 3AH default 00H
Bit Description
7~0 Watchdog timer counter value, byte 1
INDEX 3BH default 00H
Bit Description
7~0 Watchdog timer counter value, byte 2
3Bh 3Ah 39h
D7……D0 D7……D0 D7……D0
Counter
Most SBit ……………………
east SBit
INDEX 3CH
default 00H
Bit Description
7 Watchdog timer time out
0: not happened
1: happened
6 Reserved
5 Reserved
4 Reserved
3 Memory Shadow A, B page function
0: disable
1: enable
2 IRQ Level trigger selection.
0: negative level trigger
1: level trigger
1 EDO DRAM timing detect mode
0: disable
1: enable
0 IDE channel selection
0: primary channel selected
1: secondary channel selected
INDEX 3DH default 00H
Bit Description
7~0 GPO signals.
When write index 73H, Bit 7~0 will sent
to SD[15:8]
INDEX 3EH
default 00H
Bit Description
7~0 GPI signals.
When REFRESHJ is active, the SD will
become input and M6117D will use
MEMRJ rising edge to latch the SD[7:0]
to Bit 7~0. Read only
INDEX 3FH
default 00H
Bit Description
7~0 When REFRESHJ is active, the SD
will become input and M6117D will use
MEMRJ rising edge to latch the SD[16:8]
to Bit 7~0. Read only.
INDEX 40H
default 00H
Bit Description
7~1 Chip select 0 channel address A[7-1].
0 1: GPCS0J enable
0: GPCS0J disable
INDEX 41H default 00H
Bit Description
7~0 Chip select 0 channel address A[15-8].
INDEX 42H default 00H
Bit Description
7~1 Chip select 0 channel mask address
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