DMP Electronics eBOX-3350MX-AP Manual do Utilizador descarregar pdf (Página 98)

Jan Yin Chan Electronics Co.,LTD. 386SX Single Chip PC

M6117D : System on a chip

DM&P

Jan Yin Chan Electronics Co,. LTD. M6117D 386SX Single Chip PC Page 97

8F-1,No.22,Wuchyuan 2RD.,Hsin Chuang city Taipei Hsien, Taiwan, R.O.C. Tel: 886-(02) 2298-0770 Fax: (02) 2299-1883

AC Characteristics (continued)

Symbol Parameter Minimum Maximum Unit Notes

BCLK2

80 MHz Clock signal

BA2, BA23, BA24, BA25, BEHJ, BELJ, ADSJ, MIOJ,

DCJ, WRJ, valid delay

10 ns NP timing

BA2, BA23, BA24, BA25, BEHJ, BELJ, ADSJ, MIOJ,

DCJ, WRJ, float delay

10 ns NP timing

BD0-BD15 Input setup time 5 ns NP timing

BD0-BD15 Input hold time 3 ns NP timing

BD0-BD15 Output valid delay 20 ns NP timing

BD0-BD15 Output float delay 11 ns NP timing

RAS[3-0]J Valid delay 15 ns DRAM timing

RAS[3-0]J Float delay 5 11 ns DRAM timing

CAS[3-0][HL]J Valid delay 16 ns DRAM timing

CAS[3-0][HL]J Float delay 3 8 ns DRAM timing

MA[11-0] Valid delay 6 ns DRAM timing

MA[11-0] Float delay 3 ns DRAM timing

WEJ Valid delay 3 ns DRAM timing

WEJ Float delay 3 8 ns DRAM timing

SA0, BHEJ Input setup time 4 ns Note 3

SA0, BHEJ Input hold time 2 ns Note 3

SA[19,0], BHEJ Output Valid delay

2 ns Note 3

SA[19,0], BHEJ Output Float delay

8 ns Note 3

SD[15-0] Output Valid delay 0 ns CPU timing

SD[15-0] Output Float delay 3 ns CPU timing

DACKJ Group Valid delay 90 ns AT timing

DACKJ Group Float delay 15 ns AT timing

RSTDRV Valid delay 5 ns CPU timing

RSTDRV Float delay 4 ns CPU timing

skew1

Time skew between ATCLK and BCLK2 9 20 ns

skew2

Time skew between CK7M and OSC14M 6 12 ns

1 2 ... 93 94 95 96 97 98 99 100 101 102 103 ... 111 112

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