386SX Single Chip PC Jan Yin Chan Electronics Co.,LTD.
DM&P M6117D : System on a chip
Page 48
Jan Yin Chan Electronics Co,. LTD. M6117D 386SX Single Chip PC
8F-1,No.22,Wuchyuan 2RD.,Hsin Chuang city Taipei Hsien, Taiwan, R.O.C. Tel: 886-(02) 2298-0770 Fax: (02) 2299-1883
MSA[7-1]. 0=compare, 1= don't care.
0 1: PS2 IRQ1 timing enable
0: disable
INDEX 43H default 00H
Bit Description
7~0 Chip select 0 channel mask address
MSA[15-8]. 0=compare, 1= don't care.
NDEX 44H default 00H
Bit Description
7~6 Reserved
5 GPCS0J qualify with ISA MEMR.
1:enable
0:disable
4 GPCS0J qualify with ISA MEMW
1:enable
0:disable
3 GPCS0J qualify with ISA IOR.
1:enable
0:disable
2 GPCS0J qualify with ISA IOW.
1:enable
0:disable
1 Configure channel 0 16/8 bits
1:enable 16 bits
0:enable 8 bits
0 Configure channel 0 address
1:enable memory address A[25-11]
0:enable IO address A[15-1]
NDEX 45H default 00H
Bit Description
7~6 Reserved
5 GPCS1J qualify with ISA MEMR.
1:enable
0:disable
4 GPCS1J qualify with ISA MEMW
1:enable
0:disable
3 GPCS1J qualify with ISA IOR.
1:enable
0:disable
2 GPCS1J qualify with ISA IOW.
1:enable
0:disable
1 Configure channel 1 16/8 bits
1:enable 16 bits
0:enable 8 bits
0 Configure channel 1 address
1:enable memory address A[25-11]
0:enable IO address A[15-1]
NDEX 46H default 00H
Bit Description
7~0 When IOR Index 46H is active, the
independent GPIO[7-0] will be latch to bit
GPI[7-0] . This is Read Only.
NDEX 47H
default 00H
Bit Description
7~0 Independent GPIO[7-0] signal output
and storage register. When write value
to this register, bit7~0 will be sent out to
GPO[7-0] pins.
INDEX 48H
default 00H
Bit Description
7~1 Chip select 1 channel address A[7-1].
0 1: GPCS1J enable
0: GPCS1J disable
INDEX 49H default 00H
Bit Description
7~0 Chip select 1 channel address A[15-8].
INDEX 4AH default 00H
Bit Description
7~1 Chip select 1 channel mask address
MSA[7-1]. 0=compare, 1= don't care.
0 Reserved
INDEX 4BH default 00H
Bit Description
7~0 Chip select 1 channel mask address
MSA[15-8]. 0=compare, 1= don't care.
INDEX 4CH default 00H
Bit Description
7~0 When IOR Index 4CH is active, the
independent GPIO[15-8] will be latch to
bit GPI[15-8] . This is Read Only.
INDEX 4DH
default 00H
Bit Description
7~0 Independent GPIO[15-8] signal output
and storage register. When write value
to this register, bit7~0 will be sent out to
GPO[15-8] pins.
INDEX 4EH default 00H
Bit Description
7~0 Program GPIOE[7-0] , when GPIOE is
set up for high , it meanings that
independent GPIO will be as GPO[7-0]
output pins .
INDEX 4FH
default 00H
Bit Description
7~0 Program GPIOE[15-8] , when GPIOE is
set up for high , it meanings that
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